1. Field
This application relates to a linear regulator circuit, a linear regulation method, and a semiconductor device.
2. Description of the Related Art
A Low Drop-Out/linear Drop-Out (LDO) regulator circuit is a type of circuit that operates based on an input voltage as a power source and outputs a constant voltage close to the input voltage. An error amplifier detects an output voltage of an output transistor and the output transistor is controlled so that a variation in the output voltage is compensated in response to a detection result of the error amplifier. In addition, there is a need to reduce the variation in the output voltage due to a variation in the input voltage with a high degree of accuracy.
FIG. 1 illustrates a typical LDO circuit discussed in Japanese Laid-open Patent Publication No. 2007-249712. In the above-presented literature, it is discussed that a variation in an output voltage Vo due to a variation in an input voltage Vi may be reduced in response to an operation of an error amplifier 100, and operations of a resistor R3 and a capacitor C3 coupled in series between a supply node of the input voltage Vi and an output terminal of the error amplifier 100. Moreover, it is discussed that a wider bandwidth may be achieved in the error amplifier 100 when a peak of a Power Supply Reduction Ratio (PSRR) characteristic is lowered.
In the LDO circuit in FIG. 1, when the output voltage Vo varies at a high frequency in a condition where an output current flowing through a load from an output transistor Tr101 is increased, operations of the error amplifier 100 and a buffer circuit 102 may be unable to respond to the variation in the output voltage Vo. Due to at least the aforementioned reason, a phase delay increases, and the increase in the phase delay may cause an oscillation in a closed-loop that includes the output transistor Tr101, the error amplifier 100, and the buffer circuit 102.
FIG. 2 illustrates another typical LDO circuit discussed in Ka Chun Kwok et al, “Pole-zero tracking frequency compensation for low dropout regulator”, Circuits and Systems, ISCAS 2002. IEEE International Symposium, vol. 4, IV-735-IV-738, 2002. In the above-presented literature, it is discussed that a P-channel MOS transistor Mc, having a resistance value which varies in response to an output voltage of the buffer circuit A2, and a capacitor Cc are coupled in series between an input voltage supply node and an output terminal of a buffer circuit A2. Moreover, it is discussed that an error amplifier having a wider bandwidth is achieved in the LDO circuit in FIG. 2.
In the LDO circuit discussed in FIG. 2, the peak of the PSRR characteristic is reduced based on the operations of the transistor Mc and the capacitor Cc. However, the peak of the PSRR characteristic is not reduced in an area where an ON-resistance of the transistor Mc does not vary linearly, that is, in a condition where an output voltage decreases due to an increase in a load.